rev. 0.02 / apr 2009 1 240pin ddr3 sdra m unbuffered dimms ** contents are subject to ch ange without prior notice. ddr3 sdram unbuffered dimms based on 2gb a version hmt351u6afr8c hmt351u7afr8c
rev. 0.02 / apr 2009 2 hmt351u6afr8c hmt351u7afr8c revision history revision no. history draft date remark 0.01 initial draft for internal review feb. 2009 preliminary 0.02 added idd specificaion apr. 2009
rev. 0.02 / apr 2009 3 hmt351u6afr8c hmt351u7afr8c table of contents 1. description 1.1 device features and ordering information 1.1.1 features 1.1.2 ordering information 1.2 speed grade & key parameters 1.3 address table 2. pin architecture 2.1 pin definition 2.2 input/output functional description 2.3 pin assignment 3. functional block diagram 3.1 4gb, 512mx64 module(2rank of x8) 3.2 4gb, 512mx72 ecc module(2rank of x8) 4. address mirroring feature 4.1 dram pin wiring for mirroring 5. absolute maximum ratings 5.1 absolute maximum dc ratings 5.2 operating temperature range 6. ac & dc operating conditions 6.1 recommended dc operating conditions 6.2 dc & ac logic input levels 6.2.1 for single-ended signals 6.2.2 for differential signals 6.2.3 differential input cross point 6.3 slew rate definition 6.3.1 for ended input signals 6.3.2 for differential input signals 6.4 dc & ac output buffer levels 6.4.1 single ended dc & ac output levels 6.4.2 differential dc & ac output levels 6.4.3 single ended output slew rate 6.4.4 differential ended output slew rate 6.5 overshoot/undershoot specification 6.6 input/output capacitance & ac parametrics 6.7 idd specifications & measurement conditions 7. electrical characteristics and ac timing 7.1 refresh parameters by device density 7.2 ddr3 standard speed bins and ac para 8. dimm outline diagram 8.1 4gb, 512mx64 module(2rank of x8) 8.2 4gb, 512mx72 ecc module(2rank of x8)
rev. 0.02 / apr 2009 4 hmt351u6afr8c hmt351u7afr8c 1. description this hynix unbuffered dual in -line memory module(dimm) series consists of 2gb a version. ddr3 sdrams in fine ball grid array(fbga) packages on a 240 pin glass-epoxy su bstrate. this ddr3 unbuffered dimm series based on 2gb m ver. provide a high performance 8 byte interface in 133.35 mm width form factor of industry standard. it is suitable for easy interchange and addition. 1.1 device features & ordering information 1.1.1 features ? vdd=vddq=1.5v ? vddspd=3.3v to 3.6v ? fully differential clock inputs (ck, /ck) operation ? differential data strobe (dqs, /dqs) ? on chip dll align dq, dqs and /dqs transition with ck transition ? dm masks write data-in at the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? programmable cas latency 6, 7, 8, 9, 10, and (11) supported ? p r o g r a m m a b l e a d d i t i v e l a t e n c y 0 , c l - 1 , a n d c l - 2 s u p ported ? programmable cas write latency (cwl) = 5, 6, 7, 8 ? programmable burst leng th 4/8 with both nibble sequential and interleave mode ? bl switch on the fly ? 8banks ? 8k refresh cycles /64ms ? ddr3 sdram package: jedec standard 82ball fbga(x4/x8)) with support balls ? driver strength selected by emrs ? dynamic on die termination supported ? asynchronous reset pin supported ? zq calibration supported ? tdqs (termination data strobe) supported (x8 only) ? write levelization supported ? auto self refresh supported ? on die thermal sensor supported (jedec optional)
rev. 0.02 / apr 2009 5 hmt351u6afr8c hmt351u7afr8c 1.1.2 ordering information part name density org. # of drams # of ranks materials ecc ts hmt351u6afr8c-g7/h9 4gb 512mx64 16 2 halogen-free none no hmt351u7afr8c-g7/h9 4gb 512mx72 18 2 halogen-free ecc yes
rev. 0.02 / apr 2009 6 hmt351u6afr8c hmt351u7afr8c 1.2 speed grade & key parameters 1.3 address table mt/s ddr3-1066 ddr3-1333 unit grade -g7 -h9 tck(min) 1.875 1.5 ns cas latency 79tck trcd(min) 13.125 13.5 ns trp(min) 13.125 13.5 ns tras(min) 37.5 36 ns trc(min) 50.625 49.5 ns cl-trcd-trp 7-7-7 9-9-9 tck hmt351u6afr8c hmt351u7afr8c organization 512m x 64 512m x 72 refresh method 8k/64ms 8k/64ms row address a0-a14 a0-a14 column address a0-a9 a0-a9 bank address ba0-ba2 ba0-ba2 page size 1kb 1kb # of rank 22 # of device 16 18
rev. 0.02 / apr 2009 7 hmt351u6afr8c hmt351u7afr8c 2. pin architecture 2.1 pin definition pin name description pin name description a0?a14 sdram address bus scl i 2 c serial bus clock for eeprom ba0?ba2 sdram bank select sda i 2 c serial bus data line for eeprom ras sdram row address strobe sa0?sa2 i 2 c slave address select for eeprom cas sdram column address strobe v dd * sdram core power supply we sdram write enable v dd q * sdram i/o driver power supply s 0?s 1 dimm rank select lines v ref dq sdram i/o reference supply cke0?cke1 sdram clock enable lines v ref ca sdram command/address reference supply odt0?odt1 on-die termination control lines v ss power supply return (ground) dq0?dq63 dimm memory data bus v ddspd serial eeprom positive power supply cb0?cb7 dimm ecc check bits nc spare pins (no connect) dqs0?dqs8 sdram data strobes (positive line of differential pair) test memory bus analysis tools (unused on memory dimms) dqs 0?dqs 8 sdram data strobes (negative line of differential pair) reset set drams to known state dm0?dm8 sdram data masks/high data strobes (x8-based x72 dimms) v tt sdram i/o termination supply ck0?ck1 sdram clocks (positive line of differential pair) rfu reserved for future use ck 0?ck 1 sdram clocks (negative line of differential pair) - - *the v dd and v dd q pins are tied common to a sing le power-plane on these designs
rev. 0.02 / apr 2009 8 hmt351u6afr8c hmt351u7afr8c 2.2 input/output functional description symbol type polarity function ck0?ck1 ck 0?ck 1 sstl differential crossing ck and ck are differential clock inputs. all the ddr3 sdram addr/cntl inputs are sampled on the crossing of positive edge of ck and negative edge of ck . output (read) data is referenc e to the crossing of ck and ck (both directions of crossing). cke0?cke1 sstl active high activates the sdram ck si gnal when high and deac tivates the ck signal when low. by deactivating the cloc ks, cke low initiates the power down mode, or the self refresh mode. s 0?s 1sstlactive low enables the associated sdram command decoder when low and disables the command decoder when high. wh en the command decoder is dis- abled, new commands are ignored but previous operations continue. this signal provides for external rank selection on systems with multiple ranks. ras , cas, we sstl active low ras , cas , and we ( along with s ) define the command being entered. odt0?odt1 sstl active high when high, termination resistance is enabled for all dq, dqs, dqs and dm pins, assuming this function is enabled in the mode register 1 (mr1). v ref dq supply reference voltage for sstl15 i/o inputs. v ref ca supply reference voltage for sstl 15 command/address inputs. v dd q supply power supply for the ddr3 sdram output buffers to provide improved noise immunity. for all current ddr3 unbuffered dimm designs, v dd q shares the same power plane as v dd pins. ba0?ba2 sstl ? selects which sdram bank of eight is activated. a0?a13 sstl ? during a bank activate command cycle, address input defines the row address (ra0?ra15). during a read or write command cycl e, address input defines the column address. in addition to the column a ddress, ap is used to invoke autopre- charge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0, ba1, ba2 defines the bank to be pre- charged. if ap is low, autoprecharge is disabled. during a precharge com- mand cycle, ap is used in conjunction with ba0, ba1, ba2 to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0, ba1 or ba2. if ap is low, ba0, ba1 and ba2 are used to define which bank to precharge. a12(bc ) is sampled during read and write commands to determine if burs t chop (on-the-fly) will be per- formed (high, no burst ch op; low, burst chopped). dq0?dq63, cb0?cb7 sstl ? data and check bit input/output pins. dm0?dm8 sstl active high dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. alth ough dm pins are input only, the dm loading matches the dq and dqs loading. v dd , v ss supply power and ground for the ddr3 sdram input buffers, and core logic. v dd and v dd q pins are tied to v dd /v dd q planes on these modules.
rev. 0.02 / apr 2009 9 hmt351u6afr8c hmt351u7afr8c 2.3 pin assignment dqs0?dqs8 dqs 0?dqs 8 sstl differential crossing data strobe for input and output data. sa0?sa2 ? these signals are tied at the system planar to either v ss or v ddspd to con- figure the serial spd eeprom address range. sda ? this bidirectional pin is used to tr ansfer data into or out of the spd eeprom. an external resistor may be connected from the sda bus line to v ddspd to act as a pullup on the system board. scl ? this signal is used to clock data into and out of th e spd eeprom. an external resistor may be connec ted from the scl bus time to v ddspd to act as a pullup on the system board. v ddspd supply power supply for spd eeprom. this supply is separate from the v dd /v dd q power plane. eeprom supply is operable from 3.0v to 3.6v. front side(left 1?60) back side(right 121?180) front side(left 61?120) back side(right 181?240) pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc 1v ref dq v ref dq 121 v ss v ss 61 a2 a2 181 a1 a1 2v ss v ss 122 dq4 dq4 62 v dd v dd 182 v dd v dd 3 dq0 dq0 123 dq5 dq5 63 ck1 ck1 183 v dd v dd 4dq1 dq1124 v ss v ss 64 ck 1ck 1184 ck0 ck0 5 v ss v ss 125 dm0 dm0 65 v dd v dd 185 ck 0ck 0 6dqs 0dqs 0 126 nc nc 66 v dd v dd 186 v dd v dd 7 dqs0 dqs0 127 v ss v ss 67 v ref ca v ref ca 187 nc nc 8 v ss v ss 128 dq6 dq6 68 nc nc 188 a0 a0 9 dq2 dq2 129 dq7 dq7 69 v dd v dd 189 v dd v dd 10 dq3 dq3 130 v ss v ss 70 a10 a10 190 ba1 2 ba1 2 11 v ss v ss 131 dq12 dq12 71 ba0 2 ba0 2 191 v dd v dd 12 dq8 dq8 132 dq13 dq13 72 v dd v dd 192 ras ras 13 dq9 dq9 133 v ss v ss 73 we we 193 s 0s 0 14 v ss v ss 134 dm1 dm1 74 cas cas 194 v dd v dd 15 dqs 1dqs 1 135 nc nc 75 v dd v dd 195 odt0 odt0 16 dqs1 dqs1 136 v ss v ss 76 s1 s1 196 a13 a13 nc = no connect; rfu = reserved future use 1. nc pins should not be connected to anything on the dimm, including bussi ng within the nc group. 2. address pins a3?a8 and ba0 and ba1 can be mirrored or not mirrored. please refer to section 4.1 for more information on mirrored addresses. symbol type polarity function
rev. 0.02 / apr 2009 10 hmt351u6afr8c hmt351u7afr8c 17 v ss v ss 137 dq14 dq14 77 odt1 odt1 197 v dd v dd 18 dq10 dq10 138 dq15 dq15 78 v dd v dd 198 nc nc 19 dq11 dq11 139 v ss v ss 79 nc nc 199 v ss v ss 20 v ss v ss 140 dq20 dq20 80 v ss v ss 200 dq36 dq36 21 dq16 dq16 141 dq21 dq21 81 dq32 dq32 201 dq37 dq37 22 dq17 dq17 142 v ss v ss 82 dq33 dq33 202 v ss v ss 23 v ss v ss 143 dm2 dm2 83 v ss v ss 203 dm4 dm4 24 dqs 2dqs 2144 nc nc 84 dqs 4dqs 4 204 nc nc 25 dqs2 dqs2 145 v ss v ss 85 dqs4 dqs4 205 v ss v ss 26 v ss v ss 146 dq22 dq22 86 v ss v ss 206 dq38 dq38 27 dq18 dq18 147 dq23 dq23 87 dq34 dq34 207 dq39 dq39 28 dq19 dq19 148 v ss v ss 88 dq35 dq35 208 v ss v ss 29 v ss v ss 149 dq28 dq28 89 v ss v ss 209 dq44 dq44 30 dq24 dq24 150 dq29 dq29 90 dq40 dq40 210 dq45 dq45 31 dq25 dq25 151 v ss v ss 91 dq41 dq41 211 v ss v ss 32 v ss v ss 152 dm3 dm3 92 v ss v ss 212 dm5 dm5 33 dqs 3dqs 3 153 nc nc 93 dqs 5dqs 5 213 nc nc 34 dqs3 dqs3 154 v ss v ss 94 dqs5 dqs5 214 v ss v ss 35 v ss v ss 155 dq30 dq30 95 v ss v ss 215 dq46 dq46 36 dq26 dq26 156 dq31 dq31 96 dq42 dq42 216 dq47 dq47 37 dq27 dq27 157 v ss v ss 97 dq43 dq43 217 v ss v ss 38 v ss v ss 158 nc cb4 98 v ss v ss 218 dq52 dq52 39 nc cb0 159 nc cb5 99 dq48 dq48 219 dq53 dq53 40 nc cb1 160 v ss v ss 100 dq49 dq49 220 v ss v ss 41 v ss v ss 161 dm8 dm8 101 v ss v ss 221 dm6 dm6 42 nc dqs 8 162 nc nc 102 dqs 6dqs 6 222 nc nc 43 nc dqs8 163 v ss v ss 103 dqs6 dqs6 223 v ss v ss 44 v ss v ss 164 nc cb6 104 v ss v ss 224 dq54 dq54 45 nc cb2 165 nc cb7 105 dq50 dq50 225 dq55 dq55 46 nc cb3 166 v ss v ss 106 dq51 dq51 226 v ss v ss 47 v ss v ss 167 nc nc 107 v ss v ss 227 dq60 dq60 front side(left 1?60) back side(right 121?180) front side(left 61?120) back side(right 181?240) pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc nc = no connect; rfu = reserved future use 1. nc pins should not be connected to anything on the dimm, including bussi ng within the nc group. 2. address pins a3?a8 and ba0 and ba1 can be mirrored or not mirrored. please refer to section 4.1 for more information on mirrored addresses.
rev. 0.02 / apr 2009 11 hmt351u6afr8c hmt351u7afr8c 48 nc nc 168 reset reset 108 dq56 dq56 228 dq61 dq61 key key 109 dq57 dq57 229 v ss v ss 49 nc nc 169 cke1/nc cke1/nc 110 v ss v ss 230 dm7 dm7 50 cke0 cke0 170 v dd v dd 111 dqs 7dqs 7 231 nc nc 51 v dd v dd 171 nc nc 112 dqs7 dqs7 232 v ss v ss 52 ba2 ba2 172 nc nc 113 v ss v ss 233 dq62 dq62 53 nc nc 173 v dd v dd 114 dq58 dq58 234 dq63 dq63 54 v dd v dd 174 a12 a12 115 dq59 dq59 235 v ss v ss 55 all all 175 a9 a9 116 v ss v ss 236 v ddspd v ddspd 56 a7 2 a7 2 176 v dd v dd 117 sa0 sa0 237 sa1 sa1 57 v dd v dd 177 a8 2 a8 2 118 scl scl 238 sda sda 58 a5 2 a5 2 178 a6 2 a6 2 119 sa2 sa2 239 v ss v ss 59 a4 2 a4 2 179 v dd v dd 120 v tt v tt 240 v tt v tt 60 v dd v dd 180 a3 2 a3 2 front side(left 1?60) back side(right 121?180) front side(left 61?120) back side(right 181?240) pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc nc = no connect; rfu = reserved future use 1. nc pins should not be connected to anything on the dimm, including bussi ng within the nc group. 2. address pins a3?a8 and ba0 and ba1 can be mirrored or not mirrored. please refer to section 4.1 for more information on mirrored addresses.
rev. 0.02 / apr 2009 12 hmt351u6afr8c hmt351u7afr8c 3.1 4gb, 512mx64 module(2rank of x8) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0 d8 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 d2 d10 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 i/o 0 i/o 1 i/o 2 i/o 3 d3 d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4 d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 i/o 0 i/o 1 i/o 2 i/o 3 d5 d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 d6 d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm7 a0?a15 a0-a15: sdrams d0?d15 a0 serial pd a1 sa0 sa1 sda ras ras : sdrams d0?d15 cas cas : sdrams d0?d15 we we : sdrams d0?d15 s 0 s 1 cke1 cke: sdrams d8?d15 ba0?ba2 ba0?ba2: sdrams d0?d15 dqs0 dqs dqs4 dqs1 dqs5 dqs2 dqs3 dm6 dqs6 dqs7 dq15 v ss d0?d15 v dd /v dd q d0?d15 d0?d15 v ref dq scl wp spd v ddspd dqs dm dqs dqs dm dqs dqs dm dqs dqs dm dqs dqs dm dqs dqs dm dqs dqs dm dqs dqs dm dqs dqs dm dqs dqs dm dqs dqs dm dqs dqs dqs 0 dqs 4 dqs 1 dqs 5 dqs 2dqs 6 dqs 3 dqs 7 odt0 odt: sdrams d0?d7 odt1 odt: sdrams d8?d15 cke0 cke: sdrams d0?d7 ck0 ck: sdrams d0?d7 ck 0 ck : sdrams d0?d7 sa2 d0?d15 v ref ca a2 ck1 ck: sdrams d8?d15 ck 1 ck : sdrams d8?d15 zq zq zq zq zq zq zq zq zq zq zq zq reset reset :sdrams d0-d3 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relation- ships must be maintained as shown. 3. dq,dm,dqs,dqs resistors;refer to associated topo logy diagram. 4. refer to section 3.1 of this document for details on address mirroring. 5. for each dram, a unique zq resistor is connected to ground.the zq resistor is 240ohm+-1% 6. one spd exists per module. d9 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm dqs dqs zq i/o 0 i/o 1 i/o 2 i/o 3 d1 i/o 4 i/o 5 i/o 6 i/o 7 dm dqs dqs zq i/o 0 i/o 1 i/o 2 i/o 3 d7 i/o 4 i/o 5 i/o 6 i/o 7 dm dqs dqs zq d15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm dqs dqs zq cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs
rev. 0.02 / apr 2009 13 hmt351u6afr8c hmt351u7afr8c 3.2 4gb, 512mx72 mo dule(2rank of x8) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 i/o 1 i/o 2 i/o 3 d0 d9 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 i/o 0 i/o 1 i/o 2 i/o 3 d1 d10 i/o 4 i/o 5 i/o 6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 d2 d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 i/o 0 i/o 1 i/o 2 i/o 3 d3 d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d4 d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 i/o 0 i/o 1 i/o 2 i/o 3 d5 d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 d6 d15 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 i/o 0 i/o 1 i/o 2 i/o 3 d7 d16 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a0?a15 a0-a15: sdrams d0?d17 ras ras : sdrams d0?d17 cas cas : sdrams d0?d17 we we : sdrams d0?d17 cke1 cke: sdrams d9?d17 ba0?ba2 ba0-ba2: sdrams d0?d17 dq15 i/o 7 i/o 7 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 i/o 0 i/o 1 i/o 2 i/o 3 d8 d17 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs8 dm8 vss d0?d17 v dd /v dd q d0?d17 d0?d17 v ref dq spd v ddspd dm cs dqs dqs dm cs dqs dqs dm dqs dqs dm dqs dqs dm cs dqs dqs dm cs dqs dqs dm dqs dqs dm dqs dqs dm cs dqs dqs dm cs dqs dqs dm dqs dqs dm dqs dqs dm cs dqs dqs dm cs dqs dqs dm dqs dqs dm dqs dqs dm cs dqs dqs dm cs dqs dqs i/o 0 i/o 0 dm0 dm4 s 0 s 1 dqs0 dqs4 dqs 0 dqs 4 dm1 dm5 dqs1 dqs5 dqs 1dqs 5 dm2 dqs2 dm6 dqs6 dqs 2 dm3 dm7 dqs3 dqs7 dqs 3 dqs 7 dqs 6 dqs 8 odt0 odt: sdrams d0?d8 odt1 odt: sdrams d9?d17 cke0 cke: sdrams d0?d8 ck0 ck: sdrams d0?d8 ck 0ck : sdrams d0?d8 d0?d17 v ref ca ck1 ck: sdrams d9?d17 ck 1ck : sdrams d9?d17 zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq reset reset :sdrams d0-d17 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relation- ships must be maintained as shown. 3. dq,cb,dm/dqs/dqs resistors;refer to associated topology diagram. 4. refer to section 3.1 of this document for details on addr ess mirroring. 5. for each dram, a unique zq resistor is connected to ground.the zq resistor is 240ohm+-1% 6. one spd exists per module. a0 spd(ts integrated) a1 sa0 sa1 sda scl event sa2 a2 event cs cs cs cs cs cs cs cs
rev. 0.02 / apr 2009 14 hmt351u6afr8c hmt351u7afr8c 4. address mirroring feature there is a via grid located under the sdrams for wiring th e ca signals (address, bank ad dress, command, and control lines) to the sdram pins. the length of the traces from the via to the sdrams places limitations on the bandwidth of the module. the shorter these traces, the higher the bandwi dth. to extend the bandwidt h of the ca bus for ddr3 modules, a scheme was defined to reduce the length of th ese traces.the pins on the sdram are defined in a manner that allows for these short trace length s. the ca bus pins in columns 2 and 8, ignoring the mechanical support pins, do not have any special functions (secondary functions). th is allows the most flexibility with these pins. these are address pins a3, a4, a5, a6, a7, a8 and bank address pins ba0 and ba1. refer to table . rank 0 sdram pins are wired straight, with no mismatch betw een the connector pin assignment and th e sdram pin assignment. some of the rank 1 sdram pins are cross wired as defined in the ta ble. pins not listed in the table are wired straight. 4.1 dram pin wiri ng for mirroring the table 4.1 illustrates the wiring in both the mirrored and non-mirrored case. the lengths of the traces to the sdram pins, is ob viously shorter. the via grid is smaller as well. connector pin sdram pin rank 0 rank 1 a3 a3 a4 a4 a4 a3 a5 a5 a6 a6 a6 a5 a7 a7 a8 a8 a8 a7 ba0 ba0 ba1 ba1 ba1 ba0
rev. 0.02 / apr 2009 15 hmt351u6afr8c hmt351u7afr8c < figure 4.1: wiring differences for mirrored and non-mirrored addresses > since the cross-wired pins have no secondary functions, ther e is no problem in normal operation. any data written is read the same way. there are limitation s however. when writing to the intern al registers with a "load mode" opera- tion, the specific address is requ ired. this requires the controll er to know if the rank is mi rrored or not. this requires a few rules. mirroring is done on 2 rank modules and can only be done on the second rank. there is not a requirement that the second rank be mirrored. there is a bit assignme nt in the spd that indicates whether the module has been designed with the mirrored feature or not. see the ddr3 ud imm spd specification for thes e details. the controller must read the spd and have the capability of de-mir roring the address when accessing the second rank. no mirroring mirroring
rev. 0.02 / apr 2009 16 hmt351u6afr8c hmt351u7afr8c 5. absolute maximum ratings 5.1 absolute maxi mum dc ratings 5.2 dram component ope rating temperature range symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.975 v v ,3 vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.975 v v ,3 vin, vout voltage on any pin relative to vss - 0.4 v ~ 1.975 v v tstg storage temperature -55 to +100 ? ? , 2 1. stresses greater than those listed under ?absolut e maximum ratings? may cause permanent damage to the device. this is a stress rating only and function al operation of the device at these or any other conditions above those indicated in the oper ational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each othe r at all times;and vref must be not greater than 0.6xvddq,when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. symbol parameter rating units notes toper normal temperature range 0 to 85 ? ,2 extended temperature range 85 to 95 ? 1,3 1. operating temperature toper is the case surface temperature on the center / top side of the dram. for measurement conditions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperat ures where all dram specifications will be supported. during operation, the dram case temperature must be maintained between 0 - 85oc under all operating conditions 3. some applications require operation of the dram in the extended temperature range between 85? and 95? case temperature. full specifications are guaranteed in this range, but the following additional conditions apply: a) refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9 s. (this double refresh requirement may not apply for some devices.) it is also possible to specify a component with 1x refresh (trefi to 7.8s) in the extend ed temperature range. please refer to supplier data sheet and/ or the dimm spd for option avail ability. b) if self-refresh operation is required in the extend ed temperature range, than it is mandatory to either use the manual self-refresh mode with extended temperature range capability (mr2 a6 = 0band mr2 a7 = 1b) or enable the optional auto self-refresh mode (mr2 a6 = 1b and mr2 a7 = 0b).
rev. 0.02 / apr 2009 17 hmt351u6afr8c hmt351u7afr8c 6. ac & dc operating conditions 6.1 recommended dc operating conditions 6.2 dc & ac logic input levels 6.2.1 dc & ac logic input levels for single-ended signals the dc-tolerance limits and ac-noise limits for the referenc e voltages vrefca and vrefdq are illustrated in figure 6.2.1. it shows a valid reference voltage vref(t) as a func tion of time. (vref stands for vrefca and vrefdq like- wise).vref(dc) is the linear average of vref(t) over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements in table 1. furthermore vref(t) may temporarily deviate from vref(dc) by no more than +/- 1% vdd. symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.500 1.575 v 1,2 vddq supply voltage for output 1.425 1.500 1.575 v 1,2 1. under all conditions, vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd abd vddq tied together. symbol parameter ddr3-1066, ddr3-1333 unit notes min max vih(dc) dc input logic high vref + 0.100 - v 1, 2 vil(dc) dc input logic low vref - 0.100 v 1, 2 vih(ac) ac input logic high vref + 0.175 - v 1, 2 vil(ac) ac input logic low vref - 0.175 v 1, 2 vrefdq(dc) reference voltage for dq, dm inputs 0.49 * vdd 0.51 * vdd v 3, 4 vrefca(dc) reference voltage for add, cmd inputs 0.49 * vdd 0.51 * vdd v 3, 4 vtt termination voltage for dq, dqs outputs vddq/2 - tbd vddq/2 + tbd v 1. for dq and dm, vref = vrefdq. for inpu t ony pins except reset#, vref = vrefca. 2. the ?t.b.d.? entries might change based on overshoot and undershoot specification. 3. the ac peak noise on vref may not allow vref to deviate from vref(dc) by more than +/-1% vdd (for reference: approx. +/- 15 mv). for reference: approx. vdd/2 +/- 15 mv.
rev. 0.02 / apr 2009 18 hmt351u6afr8c hmt351u7afr8c < figure 6.2.1: illustration of vref(dc) tolerance an d vref ac-noise limits > the voltage levels for setup and hold time measurements vih(ac), vih(dc), vil(ac) and vil(dc) are dependent on vref. "vref " shall be understood as vref(dc), as defined in figure 6.2.1 this clarifies, that dc-variations of vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is me asured. system timing and voltage budgets need to account for vref(dc) deviations from the optimum positi on within the data-eye of the input signals. this also clarifies that the dram setup/ hold specification and derating values ne ed to include time and voltage associ- ated with vref ac-noise. timing and volt age effects due to ac-noise on vref up to the specified limit (+/-1% of vdd) are included in dram timings and their associated deratings. 6.2.2 dc & ac logic input leve ls for differential signals note1: refer to ?overshoot and undershoot specification section 6.5 on 26 page symbol parameter ddr3-1066, ddr3-1333 unit notes min max vihdiff differential input logic high + 0.200 - v 1 vildiff differential input logic low - 0.200 v 1 vdd vss vdd/2 v ref(dc) v ref ac-noise voltage time v ref(dc)max v ref(dc)min v ref (t)
rev. 0.02 / apr 2009 19 hmt351u6afr8c hmt351u7afr8c 6.2.3 differential inpu t cross point voltage to guarantee tight setup and hold times as well as output skew parameters wi th respect to clock and strobe, each cross point voltage of differential inpu t signals (ck, ck# and dqs, dqs#) must meet the requirements in table 6.2.3 the differential input cross point voltage vix is measured from the actual cross point of tr ue and complement signal to the midlevel between of vdd and vss. < figure 6.2.3 vix definition > < table 6.2.3: cross point voltage for di fferential input signals (ck, dqs) > symbol parameter ddr3-1066, ddr3-1333 unit notes min max v ix differential input cross point voltage relative to vdd/2 - 150 + 150 mv vdd vss vdd/2 v ix v ix v ix ck#, dqs# ck, dqs
rev. 0.02 / apr 2009 20 hmt351u6afr8c hmt351u7afr8c 6.3 slew rate definitions 6.3.1 for single ended input signals - input slew rate for input setup time (tis) and data setup time (tds) setup (tis and tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref and the first crossing of vih(ac)min. setup (tis and tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref and the first crossing of vil(ac)max. - input slew rate for input hold ti me (tih) and data hold time (tdh) hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of vref. hold (tih and tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih( dc)min and the first crossing of vref. < table 6.3.1: single-ended input slew rate definition > description measured defined by applicable for min max input slew rate for rising edge vref vih(ac)min vih(ac)min-vref delta trs setup (tis, tds) input slew rate for falling edge vref vil(ac)max vref-vil(ac)max delta tfs input slew rate for rising edge vil(dc)max vref vref-vil(dc)max delta tfh hold (tih, tdh) input slew rate for falling edge vih(dc)min vref vih(dc)min-vref delta trh delta tfs delta trs vih(ac)min vih(dc)min vil(dc)max vil(ac)max vrefdq or vrefca part a: set up single ended input voltage(dq,add, cmd)
rev. 0.02 / apr 2009 21 hmt351u6afr8c hmt351u7afr8c < figure 6.3.1: input nominal slew rate definition for single-ended signals > 6.3.2 differential input signals input slew rate for differential signals (ck, ck# and dqs, dqs#) are defined and measured as shown in below table and figure . note: the differential signal (i.e. ck-ck and dqs-dq s) must be linear between these thresholds. description measured defined by min max differential input slew rate for rising edge (ck-ck and dqs-dqs) vildiffmax vihdiffmin vihdiffmin-vildiffmax deltatrdiff differential input slew rate for falling edge (ck-ck and dqs-dqs) vihdiffmin vildiffmax vihdiffmin-vildiffmax deltatfdiff part b: hold delta tfh delta trh vih(ac)min vih(dc)min vil(dc)max vil(ac)max vrefdq or vrefca single ended input voltage(dq,add, cmd)
rev. 0.02 / apr 2009 22 hmt351u6afr8c hmt351u7afr8c < figure 6.3.2: differential input slew ra te definition for dqs,dqs# and ck,ck# > 6.4 dc & ac output buffer levels 6.4.1 single ended dc & ac output levels below table shows the output levels used for measurements of single ended signals. symbol parameter ddr3-1066, 1333 unit notes voh(dc) dc output high measurement level (for iv curve linearity) 0.8 x vddq v vom(dc) dc output mid measurement level (for iv curve linearity) 0.5 x vddq v vol(dc) dc output low measurement level (for iv curve linearity) 0.2 x vddq v voh(ac) ac output high measurement level (for output sr) vtt + 0.1 x vddq v 1 vol(ac) ac output low measurement level (for output sr) vtt - 0.1 x vddq v 1 1. the swing of ? 1 x vddq is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to vtt = vddq / 2. delta tfdiff delta trdiff vihdiffm in vildiffm ax 0 differential input voltage (i.e. dqs-dqs; ck-ck)
rev. 0.02 / apr 2009 23 hmt351u6afr8c hmt351u7afr8c 6.4.2 differential dc & ac output levels below table shows the output levels used for measurements of differential signals. 6.4.3 single ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between vol(ac) and voh(ac) for single ende d signals as shown in belo w table and figure 6.4.3. note: output slew rate is verified by design and characte rization, and may not be su bject to production test. < figure 6.4.3: single ended output slew rate definition > symbol parameter ddr3-1066, 1333 unit notes vohdiff (ac) ac differential output high measurement level (for output sr) + 0.2 x vddq v 1 voldiff (ac) ac differential output low measurement level (for output sr) - 0.2 x vddq v 1 1. the swing of ? 0.2 x vddq is based on appro ximately 50% of the static differential output high or low swingwith a driver impeda nce of 40?? and an effective test load of 25?? to vtt = vddq/2 at each of the differential output description measured defined by from to single ended output slew rate for rising edge vol(ac) voh(ac) voh(ac)-vol(ac) deltatrse single ended output slew rate for falling edge voh(ac) vol(ac) voh(ac)-vol(ac) deltatfse delta tfse delta trse voh(ac) vol(ac) v ? single ended output voltage(l.e.dq)
rev. 0.02 / apr 2009 24 hmt351u6afr8c hmt351u7afr8c *** description: sr: slew rate q: query output (like in dq, which stands for data-in, query-output) for ron = rzq/7 setting < table 6.4.3: output slew rate (single-ended) > 6.4.4 differential output slew rate with the reference load for timing measurements, output sl ew rate for falling and rising edges is defined and mea- sured between voldiff(ac) and vohdiff(ac) for differentia l signals as shown in below table and figure 6.4.4 note: output slew rate is verified by design and charac terization, and may not be subject to production test. < figure 6.4.4: differential output slew rate definition > parameter symbol ddr3-1066 ddr3-1333 units min max min max single-ended output slew rate srqse 2.5 5 2.5 5 v/ns description measured defined by from to differential output slew rate for rising edge voldiff(ac) vohdiff(ac) vohdiff(ac)-voldiff(ac) deltatrdiff differential output slew rate for falling edge vohdiff(ac) voldiff(ac) vohdiff(ac)-voldiff(ac) deltatfdiff delta tfdiff delta trdiff voldiff(ac) o differential output voltage(i.e. dqs-dqs) vohdiff(ac)
rev. 0.02 / apr 2009 25 hmt351u6afr8c hmt351u7afr8c ***description: sr: slew rate q: query output (like in dq, which stands for data-in, query-output) diff: differential signals for ron = rzq/7 setting < table 6.6.4: differential output slew rate > 6.5 overshoot and undershoot specifications 6.5.1 address and control overshoot and undershoot specifications < table 6.5.1: ac overshoot/undershoot sp ecification for address and control pins > < figure 6.5.1: address and control overshoot and undershoot definition > parameter symbol ddr3-1066 ddr3-1333 units min max min max differential output slew rate srqdiff 5 10 5 10 v/ns description specification ddr3-1066 ddr3-1333 maximum peak amplitude allowed for overshoot area (see figure) 0.4v 0.4v maximum peak amplitude allowed for undershoot area (see figure) 0.4v 0.4v maximum overshoot area above vdd (see figure) 0.5 v-ns 0.4 v-ns maximum undershoot area below vss (see figure) 0.5 v-ns 0.4 v-ns maximum amplitude overshoot area vdd vss volts (v) maximum amplitude undershoot area time (ns)
rev. 0.02 / apr 2009 26 hmt351u6afr8c hmt351u7afr8c 6.5.2 clock,data,strobe and mask overshoot and undershoot specifications < table 6.5.2: ac overshoot/undershoot specification for clock, data, strobe and mask > < figure 6.5.2: clock, data, strobe and mask overshoot and undershoot definition > description specification ddr3-1066 ddr3-1333 maximum peak amplitude allowed for overshoot area (see figure) 0.4v 0.4v maximum peak amplitude allowed for undershoot area (see figure) 0.4v 0.4v maximum overshoot area above vddq (see figure) 0.19 v-ns 0.15 v-ns maximum undershoot area below vssq (see figure) 0.19 v-ns 0.15 v-ns m axim um am plitude overshoot area vddq vssq maximum amplitude undershoot area time (ns) clock, data strobe and mask overshoot and undershoot definition volts (v)
rev. 0.02 / apr 2009 27 hmt351u6afr8c hmt351u7afr8c 6.6 pin capacitance parameter symbol ddr3-1066 ddr3-1333 units notes min max min max input/output capacitance (dq, dm, dqs, dqs#, tdqs, tdqs#) c io tbd tbd tbd tbd pf 1,2,3 input capacitance, ck and ck# c ck tbd tbd tbd tbd pf 2,3,5 input capacitance delta ck and ck# c dck tbd tbd tbd tbd pf 2,3,4 input capacitance (all other input-only pins) c i tbd tbd tbd tbd pf 2,3,6 input capacitance delta, dqs and dqs# c ddqs tbd tbd tbd tbd pf 2,3,12 input capacitance delta (all ctrl input-only pins) c di_ctrl tbd tbd tbd tbd pf 2,3,7,8 input capacitance delta (all add/cmd input-only pins) c di_add_ cmd tbd tbd tbd tbd pf 2,3,9, 10 input/output capacitance delta (dq, dm, dqs, dqs#) c dio tbd tbd tbd tbd pf 2,3,11 notes: 1. tdqs/tdqs# are not necessarily input function but since tdqs is sharing dm pin and the parasitic characterization of tdqs/tdqs# should be close as much as possible, cio&cdio requirement is applied (recommend deleting note or changing to ?although the dm, tdqs and tdqs# pins have different functions, the loading matches dq and dqs.?) 2. this parameter is not subject to production test. it is verified by design and characterization. input capacitance is measured according to jep147(?procedure for measuring input capacitance using a vector network analyzer(vna)?) with vdd, vddq, vss,vssq applied an d all other pins floating (except the pin under test, cke, reset# and odt as necessary). vdd=vddq=1.5v, vbias=vdd/2 and on-die termination off. 3. this parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. absolute value of c ck -c ck #. 5. the minimum c ck will be equal to the minimum c i . 6. input only pins include: odt, cs, cke, a0-a15, ba0-ba2, ras#, cas#, we#. 7. ctrl pins defined as odt, cs and cke. 8. c di_ctrl =c i (cntl) - 0.5 * c i (clk) + c i (clk#)) 9. add pins defined as a0-a15, ba0-ba2 and cmd pins are defined as ras#, cas# and we#. 10. c di_add_cmd =c i (add_cmd) - 0.5*(c i (clk)+c i (clk#)) 11. c dio =c io (dq) - 0.5*(c io (dqs)+c io (dqs#)) 12. absolute value of c io (dqs) - c io (dqs#)
rev. 0.02 / apr 2009 28 hmt351u6afr8c hmt351u7afr8c 6.7 idd specifications(t case : 0 to 95 o c) 4gb, 512m x 64 u-dimm: hmt351u6afr8c 4gb, 512m x 72 u-dimm: hmt351u7afr8c symbol ddr3 1066 ddr3 1333 unit note idd0 960 1040 ma idd1 1040 1120 ma idd2n 720 800 ma idd2nt 800 880 ma idd2p0 192 192 ma idd2p1 480 560 ma idd2q 720 800 ma idd3n 880 960 ma idd3p 560 560 ma idd4r 1480 1640 ma idd4w 1520 1680 ma idd5b 2040 2080 ma idd6 192 192 ma idd6et 240 240 ma idd6tc 240 240 ma idd7 2040 2240 ma symbol ddr3 1066 ddr3 1333 unit note idd0 1080 1170 ma idd1 1170 1260 ma idd2n 810 900 ma idd2nt 900 990 ma idd2p0 216 216 ma idd2p1 540 630 ma idd2q 810 900 ma idd3n 990 1080 ma idd3p 630 630 ma idd4r 1665 1845 ma idd4w 1710 1890 ma idd5b 2295 2340 ma idd6 216 216 ma idd6et 270 270 ma idd6tc 270 270 ma idd7 2295 2520 ma
rev. 0.02 / apr 2009 29 hmt351u6afr8c hmt351u7afr8c 6.7 idd measurement conditions in this chapter, idd and iddq measurement conditions such as test load and patterns are defined. figure 1. shows the setup and test load for idd and iddq measurements. ? idd currents (such as idd0, idd1, idd2n, idd2nt, i dd2p0, idd2p1, idd2q, idd3n, idd3p, idd4r, idd4w, idd5b, idd6, idd6et, idd6tc and i dd7) are measured as time-averaged cu rrents with all vdd balls of the ddr3 sdram under test tied together. any iddq current is not included in idd currents. ? iddq currents (such as iddq2nt and iddq4r) are measur ed as time-averaged currents with all vddq balls of the ddr3 sdram under test tied together. any i dd current is not included in iddq currents. attention: iddq values cannot be di rectly used to calculate io power of the ddr3 sdram. they can be used to support correlation of simulated io power to actual io po wer as outlined in figure 2. in dram module application, iddq cannot be measured separately since vdd and vddq are using one merged-power layer in module pcb. for idd and iddq measurements, the following definitions apply: ? ?0? and ?low? is defined as vin <= v ilac(max). ? ?1? and ?high? is defined as vin >= v ihac(max). ? ?floating? is defined as inputs are vref - vdd/2. ? timing used for idd and iddq me asurement-loop patterns are provided in table 1 on page 26. ? basic idd and iddq measurement conditi ons are described in table 2 on page 26. ? detailed idd and iddq meas urement-loop patterns are described in table 3 on page 30 through table 10 on page 36. ? idd measurements are done after properly initializing the ddr3 sdram. this includes but is not limited to setting ron = rzq/7 (34 ohm in mr1); qoff = 0 b (output buffer enabled in mr1); rtt_nom = rzq/6 (40 ohm in mr1); rtt_wr = rzq/2 (120 ohm in mr2); tdqs feature disabled in mr1 ? attention: the idd and iddq measurement-loop patterns need to be executed at least one time before actual idd or iddq measur ement is started. ? define d = {cs , ras , cas , we }:= {high, low, low, low} ? define d = {cs , ras , cas , we }:= {high, high, high, high}
rev. 0.02 / apr 2009 30 hmt351u6afr8c hmt351u7afr8c figure 1 - measurement setup and test load for idd and iddq (optional) measurements [note: dimm level output test load condition may be different from above] figure 2 - correlation from simulated channel io power to actual channel io power supported by iddq measurement v dd ddr3 sdram v ddq reset ck/ck dqs, dqs cs ras , cas , we a, ba odt zq v ss v ssq dq, dm, tdqs, tdqs cke r tt = 25 ohm v ddq /2 i dd i ddq (optional) application specific memory channel environment channel io power simulation iddq simulation iddq simulation channel io power number iddq test load correction
rev. 0.02 / apr 2009 31 hmt351u6afr8c hmt351u7afr8c table 1 -timings used for idd and iddq measurement-loop patterns table 2 -basic idd and iddq measurement conditions symbol ddr3-1066 ddr3-1333 unit 7-7-7 9-9-9 t ck 1.875 1.5 ns cl 7 9 nck n rcd 79nck n rc 27 33 nck n ras 20 24 nck n rp 79nck n faw x4/x8 20 20 nck x16 27 30 nck n rrd x4/x8 4 4 nck x16 6 5 nck n rfc -512mb 48 60 nck n rfc -1 gb 59 74 nck n rfc - 2 gb 86 107 nck n rfc - 4 gb 160 200 nck n rfc - 8 gb 187 234 nck symbol description i dd0 operating one bank active-precharge current cke: high; external clock: on; tck, nrc, nras, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : high between act and pre; command, address, bank addre ss inputs: partially toggling according to table 3 on page 30; data io: floating; dm: stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see table 3 on page 30); outp ut buffer and rtt: enabl ed in mode registers b) ; odt signal: stable at 0; pattern details: see table 3 on page 30 i dd1 operating one bank active-precharge current cke: high; external clock: on; tck, nrc, nras, nrcd, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : high between act, rd and pre; command, address; bank address inputs, data io: partially toggling according to table 4 on page 31; dm: stable at 0; ba nk activity: cycling with on bank active at a time: 0,0,1,1,2,2,... (see table 4 on pa ge 31); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 4 page 31
rev. 0.02 / apr 2009 32 hmt351u6afr8c hmt351u7afr8c i dd2n precharge standby current cke: high; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling a ccording to table 5 on page 32; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5 on page 32 i dd2nt precharge standby odt current cke: high; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling a ccording to table 6 on page 32; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: toggling according to table 6 on page 32; pattern details: see table 6 on page 32 i ddq2nt (optional ) precharge standby odt iddq current same definition like for idd2nt, however meas uring iddq current instead of idd current i dd2p0 precharge power-down current slow exit cke: low; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io : floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; precharge power down mode: slow exit c) i dd2p1 precharge power-down current fast exit cke: low; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io : floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; precharge power down mode: fast exit c) i dd2q precharge quiet standby current cke: high; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i ddq4r (optional ) operating burst read iddq current same definition like for idd4r, however meas uring iddq current instead of idd current
rev. 0.02 / apr 2009 33 hmt351u6afr8c hmt351u7afr8c i dd3n active standby current cke: high; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling a ccording to table 5 on page 32; data io: floating; dm: stable at 0; bank activity: all banks open; ou tput buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5 on page 32 i dd3p active power-down current cke: low; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i dd4r operating burst read current cke: high; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : high between rd; command, address, bank address i nputs: partially toggling according to table 7 on page 33; data io: seamless read data burst with different data betw een one burst and the next one according to table 7 on page 33; dm: stable at 0; bank activity: al l banks open, rd commands cycling through banks: 0,0,1,1,2,2,...(see tabl e 7 on page 33); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 7 on page 33 i dd4w operating burst write current cke: high; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : high between wr; command, address, bank address i nputs: partially toggling according to table 8 on page 34; data io: seamless read data burst with different data betw een one burst and the next one according to table 8 on page 34; dm: stable at 0; bank activity: all banks open, wr commands cycling through banks: 0,0,1,1,2,2,...(see tabl e 8 on page 34); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at high; pattern details: see table 8 on page 34 i dd5b burst refresh current cke: high; external clock: on; tck, cl, nrfc: see table 1 on page 26; bl: 8 a) ; al: 0; cs : high between ref; command, address, bank addr ess inputs: partially toggling according to table 9 on page 35; data io: floating; dm: stable at 0; bank activity: ref command every nref (see table 9 on page 35); out- put buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 9 on page 35
rev. 0.02 / apr 2009 34 hmt351u6afr8c hmt351u7afr8c a) burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b b) output buffer enable: set mr1 a[12] = 0b; set mr1 a[ 5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b c) precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12 = 1b for fast exit d) auto self-refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature e) self-refresh temperature range (srt): set mr2 a7 = 0b for normal or 1b for extended temperature range f) refer to dram supplier data sheet and/ or dimm spd to determine if optional features or requirements are supported by ddr3 sdram device i dd6 self-refresh current: normal temperature range t case : 0 - 85 o c; auto self-refre sh (asr): disabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs , com- mand, address, bank address inputs, data io: floati ng; dm: stable at 0; bank activity: self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: floating i dd6et self-refresh current: extended temperature range (optional) f) t case : 0 - 95 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): extend- ed e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs , command, address, bank address i nputs, data io: floating; dm: stabl e at 0; bank activity: extended temperature self-refresh oper ation; output buffer and rtt: enabled in mode registers b) ; odt signal: floating i dd6tc auto self-refresh current (optional) f) t case : 0 - 95 o c; auto self-refre sh (asr): enabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs , com- mand, address, bank address inputs, data io: floa ting; dm: stable at 0; bank activity: auto self- refresh operation; output buffer a nd rtt: enabled in mode registers b) ; odt signal: floating i dd7 operating bank interleave read current cke: high; external clock: on; tck, nrc, nras, nrcd, nrrd, nfaw, cl: see table 1 on page 26; bl: 8 a) ; al: cl-1; cs : high between act and rda; command, addre ss, bank address inputs: partially tog- gling according to table 10 on page 36; data io: re ad data burst with different da ta between one burst and the next one according to table 10 on page 36; dm: stable at 0; bank activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee table 10 on page 36; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 10 on page 36
rev. 0.02 / apr 2009 35 hmt351u6afr8c hmt351u7afr8c table 3 - idd0 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 0 0 - ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until nrc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 00 00 0 0 f 0 - ... repeat pattern 1...4 until 1*nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern 1...4 until 2*nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 0.02 / apr 2009 36 hmt351u6afr8c hmt351u7afr8c table 4 - idd1 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise floating. b) burst sequence driven on each dq signal by read command. outside burst operation, dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 00000 0 0 - ... repeat pattern 1...4 until nrcd - 1, truncate if necessary nrcd rd 0 1 0 1 0 0 00 0 0 0 0 0000000 0 ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until nrc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1,2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3,4 d , d 1111 0 00000 f 0 - ... repeat pattern nrc + 1,...4 until n rc + nrce - 1, truncate if necessary 1*nrc+nrcd rd 0 1 0 1 0 0 00 0 0 f 0 0011001 1 ... repeat pattern nrc + 1,...4 until nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern nrc + 1,...4 until *2 nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 0.02 / apr 2009 37 hmt351u6afr8c hmt351u7afr8c table 5 - idd2n and idd3n measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. table 6 - idd2nt and iddq2n t measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d 10000000000 - 1 d 1000000 0 0 00 - 2d 111100000f0 - 3d 111100000f0 - 1 4-7 repeat sub-loop 0, use ba[2:0] = 1 instead 2 8-11 repeat sub-loop 0, use ba[2:0] = 2 instead 3 12-15 repeat sub-loop 0, use ba[2:0] = 3 instead 4 16-19 repeat sub-loop 0, use ba[2:0] = 4 instead 5 20-23 repeat sub-loop 0, use ba[2:0] = 5 instead 6 24-17 repeat sub-loop 0, use ba[2:0] = 6 instead 7 28-31 repeat sub-loop 0, use ba[2:0] = 7 instead ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 1111 0 0 0 0 0 f 0 - 3d 1111 0 0 0 0 0 f 0 0000000 0 1 4-7 repeat sub-loop 0, but odt = 0 and ba[2:0] = 1 2 8-11 repeat sub-loop 0, but odt = 1 and ba[2:0] = 2 3 12-15 repeat sub-loop 0, but odt = 1 and ba[2:0] = 3 4 16-19 repeat sub-loop 0, but odt = 0 and ba[2:0] = 4 5 20-23 repeat sub-loop 0, but odt = 0 and ba[2:0] = 5 6 24-17 repeat sub-loop 0, but odt = 1 and ba[2:0] = 6 7 28-31 repeat sub-loop 0, but odt = 1 and ba[2:0] = 7
rev. 0.02 / apr 2009 38 hmt351u6afr8c hmt351u7afr8c table 7 - idd4r and iddq24 rmeasurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise floating. b) burst sequence driven on each dq signal by read command. outside burst operation, dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 rd 0 1 0 1 0 0 00 0 0 0 0 000000 00 1d100000000000- 2,3 d ,d 1111 0 0000 0 0 0 - 4rd0101000000f0 001100 11 5d1000000000f0- 6,7 d ,d 1111 0 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7
rev. 0.02 / apr 2009 39 hmt351u6afr8c hmt351u7afr8c table 8 - idd4w measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to wr commands, otherwise floating. b) burst sequence driven on each dq signal by write command. outside burst operation, dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 wr 0 1 0 0 1 0 00 0 0 0 0 000000 00 1d100010000000- 2,3 d ,d 1111 1 0000 0 0 0 - 4wr0100100000f0 001100 11 5d1000100000f0- 6,7 d ,d 1111 1 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7
rev. 0.02 / apr 2009 40 hmt351u6afr8c hmt351u7afr8c table 9 - idd5b measur ement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 ref 0 0 0 1 0 0 0 0 0 0 0 - 11.2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 f 0 - 5...8 repeat cycles 1. ..4, but ba[2:0] = 1 9...12 repeat cycles 1. ..4, but ba[2:0] = 2 13...16 repeat cycles 1...4, but ba[2:0] = 3 17...20 repeat cycles 1...4, but ba[2:0] = 4 21...24 repeat cycles 1...4, but ba[2:0] = 5 25...28 repeat cycles 1...4, but ba[2:0] = 6 29...32 repeat cycles 1...4, but ba[2:0] = 7 2 33...nrfc-1 repeat sub-loop 1, until nrfc - 1. truncate, if necessary.
rev. 0.02 / apr 2009 41 hmt351u6afr8c hmt351u7afr8c table 10 - idd7 meas urement-loop pattern a) attention! sub-loops 10-19 have inverse a[6:3] pattern and data pattern than sub-loops 0-9 a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise floating. b) burst sequence driven on each dq signal by read command. outside burst operation, dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1 rda 0 1 0 1 0 0 00 1 0 0 0 00000000 2d100000000000- ... repeat above d command until nrrd - 1 1 nrrd act 0 0 1 1 0 1 00 0 0 f 0 - nrrd+1 rda 0 1 0 1 0 1 00 1 0 f 0 00110011 nrrd+2 d 1 0 0 0 0 1 00 0 0 f 0 - ... repeat above d command until 2* nrrd - 1 2 2*nrrd repeat sub-loop 0, but ba[2:0] = 2 3 3*nrrd repeat sub-loop 1, but ba[2:0] = 3 4 4*nrrd ... d1000030000f0 - assert and repeat above d command until nfaw - 1, if necessary 5 nfaw repeat sub-loop 0, but ba[2:0] = 4 6 nfaw+nrrd repeat sub-loop 1, but ba[2:0] = 5 7 nfaw+2*nrrd repeat sub-loop 0, but ba[2:0] = 6 8 nfaw+3*nrrd repeat sub-loop 1, but ba[2:0] = 7 9 nfaw+4*nrrd ... d1000070000f0 - assert and repeat above d command until 2* nfaw - 1, if necessary 10 2*nfaw+0 act 0 0 1 1 0 0 00 0 0 f 0 - 2*nfaw+1 rda 0 1 0 1 0 0 00 1 0 f 0 00110011 2&nfaw+2 d1000000000f0 - repeat above d command until 2* nfaw + nrrd - 1 11 2*nfaw+nrrd act 0 0 1 1 0 1 00 0 0 0 0 - 2*nfaw+nrrd+1 rda 0 1 0 1 0 1 00 1 0 0 0 00000000 2&nfaw+nrrd+ 2 d100001000000 - repeat above d command until 2* nfaw + 2* nrrd - 1 12 2*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 2 13 2*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 3 14 2*nfaw+4*nrrd d100000000000 - assert and repeat above d command until 3* nfaw - 1, if necessary 15 3*nfaw repeat sub-loop 10, but ba[2:0] = 4 16 3*nfaw+nrrd repeat sub-loop 11, but ba[2:0] = 5 17 3*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 6 18 3*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 7 14 3*nfaw+4*nrrd d100000000000 - assert and repeat above d command until 4* nfaw - 1, if necessary
rev. 0.02 / apr 2009 42 hmt351u6afr8c hmt351u7afr8c 7. electrical characteristics and ac timing 7.1 refresh parameters by device density parameter symbol 512mb 1gb 2gb 4gb 8gb units ref command to act or ref command time trfc 90 110 160 300 350 ns average periodic refresh interval trefi 0 c < t case < 85 c 7.8 7.8 7.8 7.8 7.8 us 85 c < t case < 95 c 3.9 3.9 3.9 3.9 3.9 us
rev. 0.02 / apr 2009 43 hmt351u6afr8c hmt351u7afr8c 7.2 ddr3 sdram standard speed bins includ e tck, trcd, trp, tr as and trc for each corresponding bin ddr3 1066 speed bin ddr3-1066f unit note cl - nrcd - nrp 7-7-7 parameter symbol min max internal read command to first data t aa 13.125 20 ns act to internal read or write delay time t rcd 13.125 ? ns pre command period t rp 13.125 ? ns act to act or ref command period t rc 50.625 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1)2)3)4)6) cwl = 6 t ck(avg) reserved ns 4) cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1)2)3)6) cwl = 6 t ck(avg) reserved ns 1)2)3)4) cl = 7 cwl = 5 t ck(avg) reserved ns 4) cwl = 6 t ck(avg) 1.875 < 2.5 ns 1)2)3)4) cl = 8 cwl = 5 t ck(avg) reserved ns 4) cwl = 6 t ck(avg) 1.875 < 2.5 ns 1)2)3) supported cl settings 6, 7, 8 n ck supported cwl settings 5, 6 n ck
rev. 0.02 / apr 2009 44 hmt351u6afr8c hmt351u7afr8c ddr3 1333 speed bin ddr3-1333h unit note cl - nrcd - nrp 9-9-9 parameter symbol min max internal read command to first t aa 13.125 20 ns act to internal read or write delay time t rcd 13.125 ? ns pre command period t rp 13.125 ? ns act to act or ref command period t rc 49.125 ? ns act to pre command period t ras 36 9 * trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1,2,3,4,7 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,7 cwl = 6 t ck(avg) reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved ns 1,2,3,4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,7 cwl = 7 t ck(avg) reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3 (optional) ns 5 supported cl settings 6, 7, 8, 9 n ck supported cwl settings 5, 6, 7 n ck
rev. 0.02 / apr 2009 45 hmt351u6afr8c hmt351u7afr8c *speed bin table notes * absolute specification (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); notes: 1. the cl setting and cwl setting resu lt in tck(avg).min and tck(avg).max requirements. when making a selection of tck(avg), both need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. 2. tck(avg).min limits: since cas latency is not purely an alog - data and strobe output are synchronized by the dll - all possible intermediate frequencies may not be gu aranteed. an application should use the next smaller jedec standard tck(avg) value (2.5, 1.875, 1.5, or 1.25 ns ) when calculating cl [nck] = taa [ns] / tck(avg) [ns], rounding up to the next ?supported cl?. 3. tck(avg).max limits: calculate tck(avg) = taa.max / cl selected and round the result ing tck(avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg).max corresponding to clselected. 4. ?reserved? settings are not allowed. user must program a different value. 5. ?optional? settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. refer to supplier?s data sheet and sp d information if and how this setting is supported. 6. any ddr3-1066 speed bin also support s functional operation at lower freque ncies as shown in the table which are not subject to production tests but verified by design/characterization. 7. any ddr3-1333 speed bin also supports functional operat ion at lower frequencies as shown in the table which are not subject to production tests bu t verified by design/characterization. 8. any ddr3-1600 speed bin also support s functional operation at lower freque ncies as shown in the table which are not subject to production tests bu t verified by design/characterization.
rev. 0.02 / apr 2009 46 hmt351u6afr8c hmt351u7afr8c 8. dimm outline diagram 8.1 512mx64 - hmt351u6afr8c 9.50 17.30 max r0.70 2 x 2.50 0.10 min 1.45 detail-a 2.10 0.15 4 x 3.00 0.10 2 x 2.30 0.10 5.175 47.00 71.00 128.95 133.35 0.35 1.00 0.3~1.0 detail - b 5.00 3.80 0.05 2.50 0.20 0.80 0.05 0.3 0.15 2.50 full r detail - a 1.27 ? 0.10 4.00 back side 30.00 front spd note) all dimensions are in milli meters unless otherwise stated. detail-b
rev. 0.02 / apr 2009 47 hmt351u6afr8c hmt351u7afr8c 8.2 512mx72 - hmt351u7afr8c 9.50 17.30 max r0.70 2 x 2.50 0.10 min 1.45 detail-a detail-b 2.10 0.15 4 x 3.00 0.10 2 x 2.30 0.10 5.175 47.00 71.00 128.95 133.35 0.35 1.00 0.3~1.0 detail - b 5.00 3.80 0.05 2.50 0.20 0.80 0.05 0.3 0.15 2.50 full r detail - a 1.27 ? 0.10 4.00 back side 30.00 front note) all dimensions are in millimeters unl ess otherwise stated. spd
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Price & Availability of HMT351U7AFR8C-H9
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